In addition, if you have, say,
Code:
then the CPU might start reading from $5674 at the ld b,a, since nothing else is modifying $5674 in the meantime.

you aren't understanding what i'm saying during the data read, you cannot read 1 byte in 1 clock cicle you must send a command of read to ram then wait and see if it isn't doing anything and only then read the byte but during the read you must slow down the bus if the ram isn't so fast as the CPU now i said you should look to the normal behaviour of a CPU go to this address and check the section of timing diagrams that's what i mean with wait state http://www.zilog.com/docs/z180/ps0140.pdf
the z80 doesn't have wait states about the intel and motorola they have T1 i don't have talked about cahe and other things

And you don't understand what I'm talking about. Firstly, the z80 does have a wait state, which idles for 4 clock cycles:

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Yes, the RAM almost always takes more than one clock cycle to read, but what Kllrnohj and I are talking about neutralizes that problem by allowing the CPU to request data from RAM before it needs it.

Raydan, you are correct that it takes a long time to read from RAM, you are INCORRECT in your claim that the CPU doesn't do anything during this period. If your claim that it just waits around for the RAM were true, we'd all be pissing away clock cycles like crazy, not to mention that the speed would be ridiculously slow. No thanks, but I happen to prefer a CPU that can go faster than ~200mhz

P4 doesn't do nothing in that period the core2duo does because it have a thing almost identical to prefetch.... that's why core2duo are realy faster... And when i first refer to wait states i'm referring to that that you see on that PDF....

No, the core 2 duo is faster because it has a better design and, most importantly, a shorter pipeline. CPU's have been doing prefetch for YEARS now, it isn't something that is new. The P4 prescott was killed by branch prediction errors in its long pipeline. Go do some research before making stupid claims like that

o.O Kllr, you Really wanted to get your message across.

Double post corrected. Thanks for pointing that out, Netham.

I really want him to stop making up information. I'm not sure where he got that crap about branch prediction being a core 2 duo only thing, as its been around for generations You would be wise to do the same <insert ult dev'r TUTORIALS plug >

Oh, and its really Out-of-order execution that allows the CPU to not wait on the ram -> http://en.wikipedia.org/wiki/Out-of-order_execution - brach prediction is somewhat similar, but for the instructions themselves rather than for RAM access (Do note that out-of-order execution has been mainstream since the Pentium Pro in 1995 )

core2duo doesn't use prefetch it uses one thing almost identical so if you point this... you are really wrong about where i get my knowledge well go to here maybe you will understand what it is... http://www.ua.pt/guiaonline/cursos/engenharia%20_computadores_telematica.asp
althouth this could be a really pain to translate it but in that case there's nothing i can do...

Core 2 Duo does use prefetch and out of order execution, as it says in this slide from Intel: http://enthusiast.hardocp.com/image.html?image=MTE1Mjc0NTAyNWtBSmh3dm5EUFJfMV8yX2wuanBn (look under "Smart Memory"

Also, do remember that the Core 2 Duo is based on the Pentium 3

here, read some more (real) info: http://enthusiast.hardocp.com/article.html?art=MTEwNiwyLCxoZW50aHVzaWFzdA==

As i said its not normal prefetch is an different type like it says improved algorithms even i know that and im portuguese...

it *is* normal prefetch thats like saying Adobe Photoshop isn't an image editing program because it has advanced algorithms. How advanced or effective it is doesn't change that fact that Core 2 Duo uses regular ol' prefetch. There isn't another name for it, its just prefetch. thats just what it is

But I digress, because you never said it didn't use normal prefetch, YOU said it didn't use prefetch. But then again, prefetch is an idea/concept, it doesn't not describe any particular implementation, so I don't know how you can have "normal" prefetch anyway, as it changes for every micro-architecture change

well forget it you will never know what is true prefetch from what it isn't....